Method and apparatus for preventing buffers from being damaged by electrical charges collected on lines connected to the buffers

ABSTRACT

An apparatus and method are provided for preventing buffers used to reduce delays on long lines of an IC from being damaged due to charge that collects on the buffers during manufacturing. In accordance with the present invention, a protection diode is included directly in at least each buffer that is used for this purpose, i.e., for the purpose of preventing delays on long lines of the IC. By including a protection diode in at least each buffer that is used for this purpose, the present invention obviates the need for having to use tools during the IC design process to determine a suitable location for a protection diode.

TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates to integrated circuits (ICs) and,more particularly, to a solution that prevents electrical charge thatcollects on long signal lines that are interrupted by buffers, orrepeaters, in an IC from damaging the transistors of the buffers.

BACKGROUND OF THE INVENTION

[0002] In ICs, very long conductive signal lines are sometimes needed toconnect certain drivers to certain receivers in the IC. Signalspropagating along these long lines are delayed due to the combination ofthe capacitance and resistance of the lines. It is known to insertbuffers, or repeaters, into the lines to reduce the signal delays. Abuffer is a device on the IC comprised of field effect transistors(FETs) that are configured to drive the signal received by the buffer toreduce the delay. Generally, the delay increases in a non-linear fashionas the length of the line increases (i.e., the increase in delay isproportional to the length of the line squared). Therefore, theinclusion of buffers along long lines is relatively common in ICsmanufactured using current IC manufacturing processes.

[0003] One of the problems associated with the use of buffers is that,when the lines are being put down during fabrication of the IC,electrical charge builds up on the lines. The process of putting linesdown includes spraying charged metal ions onto the IC wafer. Thesecharged ions collect on the gates of the transistors of the buffers andcan punch holes in the gate oxide of the FETs, which damages therepeaters. One known solution to this problem is to fabricate diodesinto the IC that are coupled to the lines at locations close to thebuffers. The diode will pull enough of the charge off of the gate of theFET to prevent damage to the FET, and thus to the buffer.

[0004] Rule checker programs, which are used to check IC designs beforethe ICs are fabricated, are capable of determining whether a protectiondiode is needed in order to protect the buffer and, if so, the locationat which the diode should be placed in the IC. One of the difficultiesassociated with using such tools to determine whether a diode is neededand, if so, where it is to be located, is that existing tools cannotalways find a location for the protection diode. ICs typically have manyblocks and layers, and there is not always a convenient location for thediode. Also, the diode should be close to the buffer, which alsopresents problems when trying to find a location for a diode.

[0005] It would be advantageous to provide a technique that ensures thata location for a protection diode always exists, that the location isclose to the buffer and that eliminates the need to use rule checkertools to determine whether a protection diode is needed.

SUMMARY OF THE INVENTION

[0006] The present invention provides a method and apparatus forpreventing buffers used to reduce delays on long lines of an IC frombeing damaged due to charge that collects on the buffers due to thecapacitance and resistance of the lines. In accordance with the presentinvention, a protection diode is included directly in at least eachbuffer that used for this purpose.

[0007] Preferably, each buffer on the IC that functions to reducelong-line delays comprises a protection diode so that it is unnecessaryto run a rules checker program or the like to determine whether aprotection diode is need and, if so, where to place it. However, a ruleschecker program can be used to determine whether a buffer needs to beprotected by a diode. Then, protection diodes could only be included inbuffers that need them. Therefore, although the present inventionobviates the need for using a rules checker program for this purpose, arules checker program can be used with the present invention if desired.The present invention also obviates problems associated with trying todetermine where to locate a protection diode, assuming that any locationcan be found for the diode.

[0008] These and other features and embodiments of the present inventionwill be described below with reference to the detailed description,drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 illustrates a block diagram of a portion of an integratedcircuit in which a buffer, or repeater, has been inserted into a longline to reduce delays in signals transmitted from a driving block to areceiving block over the line.

[0010]FIG. 2 illustrates a block diagram of the buffer shown in FIG. 1having a diode therein that collects some of the charge on the line toprevent all of the charge from collecting on the gates of thetransistors that are comprised by the buffer.

[0011]FIG. 3 is a schematic diagram of the buffer shown in FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

[0012]FIG. 1 illustrates a block diagram of a portion 1 of an integratedcircuit in which a buffer 10, or repeater, has been included in a longline 3 to reduce delays in signals transmitted from a driving block 4 toa receiving block 5 over the line 3. As stated above, it is known in theart to connect a protection diode to the line 3 at some location betweenthe driving block 4 and the buffer 10 near the buffer 10. As statedabove, determining whether a protection diode is needed and the locationat which the protection diode should be formed is a task that, until thepresent invention, needed to be performed in order to protect thebuffer. Although rule checker programs enable this task to becomputationally performed, thus making the task easier for the designer,the task nevertheless had to be performed as part of the design process.Also, as indicated above, rule checker programs are not alwayssuccessful at finding a location for a protection diode.

[0013] In accordance with the present invention, the protection diode 20is comprised in the buffer 10 itself, as shown in FIG. 2. Preferably,each buffer on the IC that functions as a repeater comprises aprotection diode so that it is unnecessary to run a rules checkerprogram or the like to determine whether a protection diode is need and,if so, where to place it. However, this does not mean that a ruleschecker program cannot be used to determine whether a buffer needs to beprotected by a diode, and then only fabricate protection diodes inbuffers that need them. Either of these techniques can be used inaccordance with the present invention.

[0014] With reference again to FIG. 2, the first inverter 21 receivesthe signal on line 3 and inverts it. The second inverter 22 re-invertsthe inverted signal back to its original state, i.e., back to the stateof the signal prior to being operated on by the buffer 10. The inverters21 and 22 simply drive the signal on line 3 in order to reduce the delaycaused by the combined capacitance and resistance (not shown) of thelong line 3. A protection diode 20 is fabricated into the buffer 10 sothat it is as close as possible to the buffer 10 and so that a rulechecker program, or some other similar tool, is not needed to determinewhere to locate the diode 20. The diode performs its intended functionof pulling charge away from the inverter 21, thereby preventing the FETs(not shown) that make up the inverter 21 from being damaged by too muchelectrical charge on the line 3.

[0015]FIG. 3 is a schematic diagram of the buffer 10 shown in FIG. 2.The diode 20 is connected to the line 3 at node 25 and is connected toground, as shown. The inverter 21 is comprised of a PFET, p1, and anNFET, n1, which have their gates 31 and 32, respectively, tied togetherat node 33. The drain 34 of p1 and the source 35 of n1 are connectedtogether at node 36. The NFET n1 has its drain 37 connected to groundand PEET p1 has its source connected to VDD. Node 36 is connected tonode 44. The gates 42 and 43 of PFET p2 and NFET n2, respectively, ofthe inverter 22 are connected together at node 44. The drain 45 of PFETp2 and the source 46 of NFET n2 are tied together at node 47. The drain48 of NFET n2 is connected to ground and the source of PFET 49 isconnected to VDD. Node 47 is the output node of the buffer 10.

[0016] The operation of the inverters 21 and 22 is straight-forward.When node 33 is low, PFET p1 turns on, pulling node 36 high. When node33 is high, NFET n1 turns on, pulling node 36 low. When node 36 is low,PFET p2 turns on, pulling node 47 high. When node 36 is high, NFET n2turns on, pulling node 47 low. Therefore, when the input to the buffer10 is high, the output to the inverter 21 goes low. When the output ofthe inverter 21, which is tied to the input of inverter 22 goes low, theoutput of inverter 22 goes high.

[0017] The manner in which a determination can be made as to the size ofthe protection diode will now be provided. The amount of charge that ametal line collects is proportional to the volume of the metal line andcan be calculated as follows:

metal_volume=metal_length*metal_width*metal_thickness   (Eq. 1)

[0018] The amount of area of a FET gates of the buffer that is availableto store the charge that collects on the gate is proportional to thearea of the gate and can be calculated as follows:

gate_area=gate_length*gate_width   (Eq. 2)

[0019] The antenna ratio is equal to the metal volume given by Equation1 divided by the gate area given by Equation 2, i.e.,

antenna_ratio=metal_volume/gate_area   (Eq. 3)

[0020] If the antenna ratio given by Equation 3 is less than aparticular number, e.g., 2000, no protection diode is needed. Theantenna ratio that determines whether or not a protection diode isneeded is process-dependent and vendor-dependent. Those skilled in theart understand the manner in which, for a given process, the antennaratio can be used to determine whether or not a protection diode isneeded. If the antenna ratio given by Equation 3 is greater than aparticular number, e.g., 2000, a protection diode is needed, and theantenna ratio can be used to determine the size of the diode needed.

[0021] For example, assuming that for a given process an antenna ratiothat exceeds 2000 indicates that a protection diode is needed, thefollowing equation gives the size of the diode needed. The size is insquare microns.

diode_area=(antenna_ratio−2000)/500   (Eq. 4)

[0022] As stated above, it is preferable to include a protection diodein each buffer. However, as shown by Equations 1-4, if desired, adetermination can be made as to whether a protection diode is needed andthe size of the diode. Then, protection diodes need only be included inbuffers that are determined to need them. The size of the protectiondiode will depend on the size of the FETs of the buffers. The size ofthe FETs of the buffers is proportional to the driving strength of thebuffers and, consequently, to the amount that the delay is reduced inthe associated line. Therefore, the size of the diodes will depend onthe characteristics of the buffers, which, in turn, depend on otherfactors, such as the process used to create the IC. Those skilled in theart will understand these relationships and dependencies and the mannerin which they should be taken into account.

[0023] It should be noted that the present invention has been describedwith reference to particular embodiments and that the present inventionis not limited to the particular embodiments described herein. Forexample, the logical arrangement of the FETs in the inverters can bealtered to achieve the same effects as those described above withreference to FIG. 3. Also, the number of FETs that make up the inverterscan be changed. For example, more FETs can be added to increase thedrive strength of the inverters, as will be understood by those skilledin the art. The present invention is also process independent and can beapplied regardless of the IC process used to create the IC, as will alsobe understood by those skilled in the art in view of the discussionprovided herein. Other modifications may also be made without deviatingfrom the scope of the present invention.

What is claimed is:
 1. An apparatus for preventing buffers used toreduce delays on relatively long conductive signal lines of an IC frombeing damaged during manufacturing of the IC, the apparatus comprising:a buffer having an input connected to one of said conductive signallines of an IC that comprises the buffer; a protection diode comprisedby said buffer, the protection diode being coupled to the input of thebuffer, the protection diode pulling at least some electrical charge offof one or more transistor gates of one or more respective transistors ofthe buffer to prevent the buffer from being damaged by too muchelectrical charge collecting on one or more transistor gates ofrespective transistors of the buffer.
 2. The apparatus of claim 1,wherein every buffer of the IC comprises a protection diode.
 3. Theapparatus of claim 1, wherein only buffers of the IC that have beendetermined to need protection diodes comprise a protection diode.
 4. Theapparatus of claim 1, wherein the size of the protection diode in termsof area is at least partially dependent on the gate area of at least oneof the transistor gates of the buffer that is available for storingelectrical charge.
 5. The apparatus of claim 1, wherein each buffercomprises two inverters, each inverter comprising at least one P fieldeffect transistor (PFET) and at least one N field effect transistors(PFET), each PFET and each NFET having a gate a source and a drain, andwherein electrical charge collects on the gates of at least the PFET andNFET of at least one of the inverters.
 6. The apparatus of claim 1,wherein each buffer comprises two inverters that utilize bipolarjunction transistor (BJT) technology.
 7. The apparatus of claim 1,wherein the size of the protection diode in terms of area is at leastpartially dependent on dimensions of the conductive signal line to whichthe buffer input is connected.
 8. The apparatus of claim 1, wherein thesize of the protection diode in terms of area is dependent on dimensionsof the conductive signal line to which the buffer input is connected andon the gate area of at least one of the transistor gates of the bufferthat is available for storing electrical charge.
 9. The apparatus ofclaim 1, wherein the size for the protection diode in terms of areadepends at least partially on the IC process used to design the IC. 10.A method for preventing buffers used to reduce delays on relatively longconductive signal lines of an IC from being damaged due to electricalcharges that collect on the buffers during manufacturing of the IC, themethod comprising the steps of: buffering one of said relatively longconductive signal lines of an IC with a buffer to reduce delays in saidone of said relatively long conductive signal lines, said buffercomprising a protection diode, the protection diode being coupled to aninput of the buffer, the protection diode pulling at least some of theelectrical charge off of one or more transistor gates of one or morerespective transistors of the buffer to prevent the buffer from beingdamaged by too much electrical charge collecting on one or moretransistor gates of respective transistors of the buffer.
 11. The methodof claim 10, wherein every buffer of the IC comprises a protectiondiode.
 12. The method of claim 10, further comprising the step ofdetermining whether a buffer needs a protection diode before including aprotection diode in the buffer, wherein only buffers of the IC that havebeen determined to need protection diodes comprise a protection diode.13. The method of claim 10, wherein the size of the protection diode interms of area is at least partially dependent on the gate area of atleast one of the transistor gates of the buffer that is available forstoring electrical charge.
 14. The method of claim 10, wherein the sizeof the protection diode in terms of area is preselected.
 15. The methodof claim 10, wherein the IC is manufactured using bipolar junctiontransistor process technology.
 16. The method of claim 10, wherein theIC is manufactured using filed effect transistor process technology. 17.The method of claim 10, wherein the size of the protection diode interms of area is at least partially dependent on dimensions of theconductive signal line to which the buffer input is connected.
 18. Themethod of claim 10, wherein the size of the protection diode in terms ofarea is dependent on dimensions of the conductive signal line to whichthe buffer input is connected and on the gate area of at least one ofthe transistor gates of the buffer that is available for storingelectrical charge.
 19. The method of claim 10, wherein the size for theprotection diode in terms of area depends at least partially on the ICprocess used to design the IC.
 20. The method of claim 11, wherein thesize for the protection diode in terms of area is preselected.